Integrated design space exploration based on power-performance trade-off using genetic algorithm

Abstract

This paper presents a novel approach for Design Space Exploration (DSE) of integrated scheduling, allocation and binding in High Level Synthesis based on user specified power consumption and execution time constraints using multi structure Genetic Algorithm (GA). A pioneering effort has been made to explore the power-performance tradeoffs related to design of VLSI applications. The new cost function comprising of execution time is useful for data pipelined applications since it considers latency, cycle time (resulting from initiation interval) and number of sets of pipelined data. The GA based DSE initiates with a novel seeding process for parents as proposed in this paper which guarantees that the final solution will be optimal/near optimal. The proposed approach when verified for number of benchmarks yielded superior results in terms of power optimization and latency compared to a recent GA based approach. Moreover, the efficiency of the proposed approach was demonstrated by the fact that the experimental results also indicated the optimized performance (or execution time for pipelined data) as well as the optimal clock frequency for implementation which the current approach was unable to find.