Integrated delay analysis of regulated ATM switch

Abstract

We present an efficient and effective method to derive the worst case delay in an ATM switch. In an ATM switch, admitting a hard real-time connection requires the delays of cells belonging to the connection meeting their deadline without violating the guarantees already provided to connections that are currently active. Previous studies have shown that the real-time connection traffic and the available service can both be described by piecewise linear functions in terms of time. By utilizing the inverse of the arrival and service functions, we obtain an efficient and effective method to complete the worst case delay of a connection to an ATM switch. We analyze and compare the performance of an ATM switch with priority driven and FIFO scheduling policies under different utilization. We also compare the performance using our proposed integrated method with the traditional independent method. From simulation experiments, we found that our method always obtains a higher admission probability and a better estimation of cell delay within an ATM switch.