Abstract
The architecture and implementation of a word processing subsystem for a real-time speech recognition system using hidden Markov models are described. The bottleneck of this system, which is the acquisition of data, is demonstrated, and an architecture that speeds up this bottleneck using on-chip dual-ported cache memories is presented. The architecture is described in a textual form, and the layout data were completely automatically generated. The chips have been fabricated through MOSIS using a 2- mu m CMOS n-well technology. The functionality of the processors was successfully tested using the scan-path test methodology. The clock rate for the scan-path test was 5 MHz to guarantee proper operation of the circuits for this clock rate. All the processors were first time working silicon.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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