Abstract
L'ouvrage montre l'importance d'une analyse de la sensibilite aux defauts dans les processus de conception des circuits integres a haute densite composants (VLSI). La modelisation des defauts dans les technologies de la microelectronique est etudiee. Sommaire : 1.Introduction. 2.Defect semantics and yield modeling. 3.Computational models for defect-sensitivity. 4.Single defect multiple layer (SDML) model. 5.Fault analysis and multiple layer critical areas. 6.Single defect single layer (SDSL) model. 7.IC Yield prediction and single layer critical areas. 8.Single vs. Multiple layer critical areas.
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