Integrated and Interconnected Array of Light-Emitting Transistors and Transistor Lasers on Silicon for Photonic Logic

Abstract

A scalable method of integrating III-V epitaxial structures onto silicon and producing a large-area array of interconnected three-terminal photonic devices in the integrated material is demonstrated. This work establishes CMOS-compatible techniques for GaAs-based active photonic material (n-InGaP/p-GaAs/n-GaAs) to be converted into a distribution of epitaxial islands with direct thermal and electrical connection to a silicon host wafer. A temporary epitaxial bonding process orients and etches modified heterojunction bipolar transistor (HBT) material into a gridded mesh of islands (collector-side up) on a silicon-based carrier wafer with device-level alignment. A subsequent epitaxial transfer creates a permanent metal-eutectic bond between the III-V islands and the silicon host wafer that serves as a uniform electrical interconnect between front-end-of-line processed CMOS and the collector terminals of a photonic chip layer. Thermal, electrical, and mechanical characterization of the integrated material is performed to ensure that the interconnect is suitable for fabrication of photonic devices into the larger-area transferred material. A separate epitaxial process for uniting passive waveguide materials to the same host wafer is then similarly performed. The result is a closely-aligned grid where each III-V island is surrounded by passive material islands. The integrated III-V islands (emitter-side up) are then patterned in unison into an array of light-emitting transistors (LET) and edge-emitting transistor lasers (TL) that are designed for efficient optical coupling into waveguides formed in the passive material, functioning together as active and passive devices in a single network. Device processing parameters are inspected and optimized to account for variations in processing on integrated (thin-film) III-V materials as compared to monolithic device processing, as well as to adhere to CMOS-compatible methods and metallization. The resulting array of three-terminal photonic devices are linked by means of a vertical electrical interconnect through the collector contact and a lateral optical interconnect aligned to the carrier-recombination quantum well (QW) in the base region. Optical and electrical testing (DC) is performed on the integrated devices both individually and as an integrated network for electrical and optical output characteristics, while a comparison to fabricated monolithic three-terminal photonic devices is utilized to relate performance of integrated active photonic devices. Initial work on high-speed testing is performed to benchmark the thermal and electrical improvements in integrated photonic devices. Simulation of the device characteristics is further employed to investigate methods to optimize optical output in relation to electrical gain and beta suppression. The techniques and processes established enable a scalable network of photonic devices for novel heterogeneously integrated electronic-photonic circuitry. This heterogeneous integration produces a platform for pairing a photonic chip layer with a CMOS host wafer such that the interconnects for electrical and optical signals allow for photonic logic designs. Figure 1