Integrated aerial image sensor: Design, modeling, and assembly

Abstract

The subject of this article is a novel integrated aerial image sensor (IAIS) system suitable for integration within the surface of an autonomous test wafer. The IAIS could be used as a lithography processing monitor, affording a “wafer’s eye view” of the process, and therefore facilitating advanced process control and diagnostics without integrating (and dedicating) the sensor to the processing equipment. The main IAIS challenge is to retrieve nanometer-scale aerial image detail, while utilizing micrometer-scale photodetector pixels. To address this problem, the authors propose a design of an on-wafer aperture mask that, when combined with an appropriate periodic aerial image, will produce a low spatial frequency interference pattern. They demonstrate a design example aimed at the 65nm technology node through TEMPEST simulation. Also they detail the IAIS modeling techniques based on Abbe’s formulation [Archiv f. Mikroskopische Anat 9, 413 (1873)]. The performance of the IAIS under different lithography settings can be predicted accordingly. The intent is to create a library that captures the aerial image to detector image correspondence in order to facilitate rapid analysis. They also examine several approaches towards the integration of charge-coupled device chips with a near field aperture mask. Capillary force assisted alignment assembly techniques appear quite promising and are being discussed in detail.