Abstract
Addressing lifetime performance degradation caused by circuit ageing has been a topic of active research for the past few years. In this paper we present a different perspective to this problem, by leveraging the presence of clock tuning elements that are commonly available in high-performance designs. By combining clock tuning elements with on-chip sensors for predicting setup/hold-time violations, we introduce a new clock tuning mechanism that operates on-the-fly and it maintains the maximum achievable performance in-system for each circuit sample affected by ageing.
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