Abstract
Recent research in computer architecture has led to the development of Reduced Instruction Set Computers (RISCs). Such computers exploit the fast execution of a low number of low-level instructions. However, two problems arise: ( i ) as the RISC instruction set architectures are completely new and use specific look-ahead techniques, optimizing code generators of compilers must be developed from scratch to allow high level language programming; ( ii ) the high execution rate and low semantic instruction content inherent to RISCs requires extremely high instruction bandwidth in order to achieve maximal throughput. In this paper we propose to apply the concept of coprocessing in the instruction path and show how this technique, in particular in the RISC-case, greatly contributes to the solution of the two above problems.
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