In-situ Monitoring for Slack Time Violation Without Performance Penalty

Abstract

High-performance requirements are forcing circuits to have lower combinational depth. At lower depth, degradation of performance can be significant due to multiplexer present in scan flip flop during functional mode. Therefore, exclusion of multiplexer from functional path has been a crucial factor for performance. Furthermore, newer technology nodes are continuously introduced to meet the demand of high-performance system on chips. However, variations, such as environmental variation (temperature) and aging variation (negative bias temperature instability) etc., affect temporal reliability significantly in recent technology nodes. Adding pessimistic timing margin to ensure the reliable working of a circuit under worst case can cause performance as well as power loss. In this paper, we propose an in-situ error prediction monitor with scan-in capability. The proposed cell uses extra master latch. During test mode, slave latch gets scan-in data from extra master latch whereas during functional mode this extra latch helps in error prediction. The proposed cell design adheres to traditional test generation and application. The detailed simulation demonstrates the effectiveness of the design.