Insights on fundamental mechanisms impacting Ge metal oxide semiconductor capacitors with high-k/metal gate stacks

Abstract

Capacitance-voltage (CV) measurements on germanium metal oxide semiconductor (MOS) structures show unusual frequency behavior compared to their silicon counterparts—a low-frequency behavior of the high-frequency CV characteristics is observed in the inversion regime, and the experimental CV curves in the depletion regime exhibit large features that have been attributed to high densities of interface defects (Dit). In this paper, an electrical model is proposed to give insights on the fundamental mechanisms impacting Ge structures from a careful analysis of these CV measurements. Thanks to this analytical model, both CV and GV (conductance-voltage) characteristics have been accurately simulated over a large range of gate voltages and frequencies. The modeling of the strong inversion regime confirms that the generation-recombination of minority carriers is assisted by bulk traps and shows that a small level of impurities in Ge—in the 1015–1016percm3 range—can explain the frequency dispersion observed in the CV curves. The modeling in the depletion regime takes into account the fast minority carrier response in Ge. This clearly shows that the filling of the interface traps by minority carriers is essential for explaining the large features observed in the weak inversion regime and consequently that common Dit extraction techniques used on Si cannot be applied any longer to Ge MOS structures.