Insertion loss-aware application mapping onto the optical Cube-Connected Cycles architecture

Abstract

Optical on-chip network provides a high-performance on-chip communication platform, while several reliability challenges, such as insertion loss and crosstalk noise may limit their scalability. In this paper, we propose an insertion loss-aware task mapping on the novel nanophotonic network-on-chip architecture based on the Cube Connected Cycles topology. A contention-free quasi-Dimension-order-Routing algorithm along with area-efficient router structure and 2D-layout are the main advantages of the proposed optical architecture. The efficiency of the proposed architecture, in terms of system-level parameters, such as throughput, average packet latency, and scalability is discussed based on several simulation scenarios. The insertion loss parameter of the proposed network, along with the reliability parameter of signal to noise ratio, are evaluated through optimized application mapping. The experimental results based on Genetic Algorithm show that our proposed network outperforms by about 5.2% and 3.9% in all benchmark applications in comparison with Mesh, and Torus topologies, respectively.