Input impedance matching optimization for adaptive low-power low-noise amplifiers

Abstract

Portable and implantable devices with wireless connectivity generate a high demand for low-power RF circuits. Biasing transistors in the subthreshold region allows significant reduction of power consumption, but calls for effective design techniques to minimize performance tradeoffs. This paper addresses one of the challenges associated with subthreshold RF low-noise amplifier (LNA) design: The input impedance of the ubiquitous CMOS inductor-degenerated common-source LNA operated in the subthreshold region is analyzed. By taking the increased impact of larger parasitic capacitances in the subthreshold region into account, the proposed input impedance equations provide more precise S11 prediction than the conventional approximation. In addition, a tuning method for the LNA's input impedance is presented to guarantee matching in the presence of manufacturing process variations. This tuning is implemented with a programmable capacitance to allow for digitally-assisted calibration. A 2.4 GHz LNA was designed in 0.18 μm CMOS technology and post-layout simulations were performed with device corner models across temperature and supply voltages variations. With these variations and ±15 % source/gate inductor tolerance, the simulated S11 (<?16 dB) of the tunable LNA is at least 8.5 dB better than for the identical reference design without tuning, while minimally affecting other performance parameters.