In-pixel ADC concept with HDR hyperbolic compression and CDS

Abstract

This paper introduces the novel concept of hyperbolic compression for a high dynamic range (HDR) image sensor pixel architecture featuring in-pixel analog to digital conversion (ADC), as well as correlated double sampling (CDS) to reduce DC offsets, reset noise and low frequency noise components. A major challenge for even such modest in-pixel signal processing is the layout space consumed and the resulting low fill-factor and the resultant degradation of image sensor quality and costly scaling. Purely to illustrate a concrete fill-factor, we present the (unfortunately non-functional) silicon realization in a 2D front side illumination (FSI) 0.35µm CMOS image sensor (CIS) and propose that the low fill-factor (30%) and pixel size (110µm×55µm) can be overcome in the near future in a back side illumination (BSI) implementation in an emerging ultra dense 3D sequential integration (3DSI) CMOS process, projecting a near 100% fill factor for a 4µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> pixel in a 5-tier 28nm technology 3DSI stack.