Abstract
High speed performance of InP/InGaAs DHBTs based on a structure with a thin n-type InP layer inserted between the base and collector layers has been investigated using a submicron-model. Compared with a structure without the thin layer, considerable improvements in the current gain frequency ( f T) and the transistor forward transit time ( τ F) have been obtained with a slight degradation in the maximum oscillation frequency ( f max) caused by increases in collector capacitance. This phenomena has given no improvement in the ECL gate delay ( τ d). F T of 102 GHz and f max of 65 GHz were predicted for a 30 nm thick base transistor with 0.5 × 2 μm 2 emitter area. τ d of 13 ps was obtained for the same structure with a collector current of 6.5 × 10 4 A/cm 2. Scaling the emitter width to reduce the capacitances has given only a marginal improvement in the gate delay.
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