Abstract

We presented an innovative composite α-Si/SiO2/Si3N4/SiO2 (α-Si/ONO) hard mask etching technology to produce sub-30nm ultrafine gate patterns. Effects of process parameters, such as the CF4/CH2F2 flow ratio, 2MHz LF power and O2 flow, on etch rates of SiO2, Si3N4 and α-Si, and on the etch selectivities between SiO2, Si3N4 and α-Si, were studied using a capacitively coupled plasma (CCP) etcher. It can be observed that the line width of ONO hard mask closely relates to etch selectivities between SiO2 and Si3N4 to α-Si. Only at appropriate etch selectivities, does hard mask opening not exert significant impact on etching profile. In this case, a low line width roughness (LWR) value of 3.3nm can be achieved.Ultrafine gate patterns that exhibit a smooth and steep etching profile with low LWR are accomplished successfully. Even if the line width is reduced from 29nm to 22nm by above 20%, the thickness of remaining ONO hard mask hardly changes. Consequently, the etching technology featuring α-Si/ONO hard mask developed in this work is capable to produce ultrafine gate patterns in the sub-30nm technology nodes.

Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call