Innovative Techniques in Comparator Designs

Abstract

This paper presents four innovative designs of comparators proposed these years. A latch-type dynamic bias adds a tail capacitor to prevent fully discharging at the pre-amplifier output nodes to reduce energy consumption. The comparator is analysed and then compared with floating inverter amplifier (FIA) type. The pre-amplifier of the FIA type adopts an inverter-based input pair by a floating reservoir capacitor, greatly boosting gm/Id and improving the energy efficiency. The edge-pursuit comparator (EPC) provides a new perspective when designing comparators. According to the input difference, it will automatically adjust the comparison energy, avoiding wasting unnecessary energy spent on coarse comparison. Finally, for the edge-race comparator (ERC), it further improves the performance of saving energy and addressing the relatively long comparison time in the EPC.