Abstract

The wafer fabrication process in semiconductor manufacturing involves thousands of sequential steps from different process modules, such as Chemical Mechanical Planarization (CMP), Chemical Vapor Deposition (CVD), Wet/Dry Etching, etc. The high complexity of the processes entails the risk of a process failure and leads to a long manufacturing cycle time and higher greenhouse gas emissions (GHG) before the wafers eventually reach the probe module for electrical tests. This is particularly evident as 3D NAND devices have been introduced into the industry as the layers are stacked vertically and more process steps are involved in the flow compared to 2D NAND. Therefore, one of the main approaches to process improvement is process simplification by restructuring the process flow to allow for less complex processes or even the elimination of steps without compromising yield and quality. In this way, wafer fabrication and the manufacturing process can be made more efficient and environmentally friendly, which not only shortens the manufacturing cycle time but also reduces the total cost per wafer (CPW) or even eliminates the capital expenses required for tool purchase in high-volume manufacturing facilities. This paper elaborates on various process evaluation methodologies and techniques by understanding the root cause of defects that motivated CMP buff insertion and defect improvement methods through cleaner chemical vapor deposition processes, optimized wet cleaning or scrubbing, or improved CMP cleaning. Some examples of such process simplification work on replacement gate (RG) NAND are discussed in this paper, such as de-ionized water (DIW) Buff CMP elimination (by upstream step Oxidation Clean optimization), Ceria based Slurry Buff CMP elimination (by improving upstream deposition cleanliness improvement), and CMP buff step with new slurry and consumable configuration for lower cost and reduction of greenhouse gas emissions.

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