Innovative and rapid design for I2C (inter-integrated circuit) interface communication of FPGA chips

Abstract

A new design flow is proposed to greatly improve the efficiency and accuracy of the HDL program design. This paper successfully completes the FPGA (Field-Programmable Gate Array) chip’s external communication I2C interface design of new design flow not traditionally one. FPGA chip is often used in mobile phones, military, aerospace or other industries. Even INTEL and Microsoft and other large companies have begun to acquire FPGA-related companies, showing its importance. But the FPGA language is written in the Hardware Description Language (HDL) which is a mechanical engineering staff obstacles. Therefore, this article makes use of the MATLAB / SIMULINK tool, which is familiar with the engineering staff, to complete the FPGA chip’s I2C interface design. The advantage is that the functional simulation and HDL program can be completed at the same time, do not have to perform the function after the simulation before designing HDL program. The traditional design wastes many times to revise back and forth between function simulation and HDL program design. Finally an experimental illustration is proposed to verify the proposed design of the I2C communication interface for an HDL program on the read and write experiments of Electrically-Erasable Programmable Read-Only Memory (EEPROM).