Inner code assisted parallel concatenated single parity check codes

Abstract

This paper proposes a novel coding scheme to improve the performance of multidimensional parallel concatenated single parity check (PCSPC) codes. The high error floor of PCSPC codes prevents clear turbo cliff to be seen in the bit‐error rate (BER) performance. Based on the product accumulate type‐I (PA‐I) coding scheme, which adds serially an accumulator to the existing PCSPC code structure, our coding scheme considers a wide range of rate‐1 recursive systematic convolutional (RSC) codes replacing the accumulator. The convergence behavior of the proposed iterative decoding is monitored and analyzed using an extrinsic information transfer (EXIT) chart. It has been revealed from the EXIT chart analysis that the proposed coding scheme has a lower convergence threshold than the PA‐I coding scheme, especially when using a lower code rate PCSPC code as the outer code. For the 2D PCSPC(3,2) code with the code rate 0.5, the proposed coding scheme has a convergence threshold of 0.47 dB, whereas the convergence threshold of the PA‐I coding scheme is 0.81 dB. The convergence threshold of the proposed coding scheme is closer to theoretical limit (0.28 dB away from the theoretical limit) than that of the PA‐I coding scheme (0.62 dB away). However, for PCSPC codes with a higher code rate, the performance improvement of the proposed coding scheme with respect to the PA‐I coding scheme becomes smaller. A series of simulations is carried out to investigate the performance of the proposed coding scheme, and the simulation results show that better performance is achieved by using the proposed coding scheme compared with the PA‐I coding scheme. The simulation results show good consistency with the convergence threshold obtained from the EXIT chart, as the difference is only within 0.34 dB in all the evaluated cases. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.