Abstract

It is difficult to implement high-resolution layer-to-layer alignment by direct inkjet printing because of the limitation of position accuracy of the common inkjet printer. The poor alignment of conventional printers generally causes large parasitic overlap capacitances between the gate and source/drain (S/D) of thin-film transistors (TFTs), which degrades device operating speeds. In this paper, a self-aligned method was proposed to minimize the parasitic overlap capacitance. In this method, a hydrophobic fluoropolymers (Cytop) coffee stripe prepared by inkjet printing was utilized to define the gate electrodes, and to dewet deposited ink droplet for self-aligned S/D electrodes. This kind of inkjet-printed self-aligned TFTs with In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.95</sub> Sc <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.05</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> channel layer have a parasitic overlap capacitance as small as 0.31-0.45 pF. The TFTs in array exhibited an on/off ratio larger than 107 and a maximum saturation mobility of 4.63 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> .

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