Abstract
Charge sharing poses a fundamental problem in the design of dynamic logic gates, which is nearly as old as digital circuit design itself. Although, many solutions are known, up to now most of them add additional complexity to a given circuit and require careful optimization of device sizes. Here we propose a simple CMOS-technology compatible transistor level solution to the charge sharing problem, employing a new class of field effect transistors with multiple independent gates (MIGFETs). Based on mixed-mode simulations in a coordinated device-circuit co-design framework, we show that their underlying device physics provides an inherent suppression of the charge sharing effect. Circuit layouts and design examples are discussed, which elucidate the fundamental differences in circuit topology to classical CMOS designs. For example it is shown that dynamic gates from MIGFET scale much better with stack height of long serial networks, leading to an increased circuit performance, while also providing higher signal stability.
Highlights
Dynamic logic is a design methodology which has been widely used in modern microprocessors, due to its benefits in terms of area, performance and power consumption over other logic families, such as static logic, pseudo-NMOS logic and complementary pass transistor logic (CPL) [1]
ELIMINATING CHARGE SHARING AT THE DEVICE LEVEL Analysis of the charge sharing event was carried out by mixed-mode TCAD simulations using a similar multiple independent gate field effect transistors (MIGFETs) layout with scaled geometries that is patternable in a technology with 24 nm minimal feature size (128 nm channel lengths, 4 individual gates of 24 nm lengths each, 6 nm silicon channel width, 5.6 nm HfO2 dielectric, corresponding to 1 nm EOT and TaN electrodes with 4.62 eV work function.) Typically, a NiSi2 Schottky contact having a work function of 4.71 eV to provide near midgap band alignment is used to realize symmetric p- and n-functionality [22]
Suppression of charge sharing, performance and topology have been evaluated based on mixed-mode simulations and logical effort analysis
Summary
Dynamic logic is a design methodology which has been widely used in modern microprocessors, due to its benefits in terms of area, performance and power consumption over other logic families, such as static logic, pseudo-NMOS logic and complementary pass transistor logic (CPL) [1]. TROMMER et al.: INHERENT CHARGE-SHARING-FREE DYNAMIC LOGIC GATES EMPLOYING TRANSISTORS volatile charge is lost during the evaluation process either by leakage across the channel or through the reverse-biased diode of the diffusion area [5] Another very specific issue to dynamic gates is the socalled charge sharing problem. As a result dynamic logic styles have become unpopular in modern microelectronics, because the signal integrity of the circuit is at risk, especially when the design does not account for possible charge sharing In this paper it will be demonstrated how a new class of transistors, the so called multiple independent gate field effect transistors (MIGFETs), can be employed to eliminate the charge sharing problem without the need for any additional circuitry.
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