Influences of the Source and Drain Resistance of the MOSFETs on the Single Event Upset Hardness of SRAM cells

Abstract

The influences of the source and drain resistance of both the nMOSFETs and pMOSFETs on the single event response of SRAM cells have been investigated by the SPICE simulations. The results show that the source and drain resistance of the nMOSFETs can increase the single event upset (SEU) hardness of a cell, whereas the source and drain resistance of the pMOSFETs result in a reduction in the SEU hardness, with the drain region of the OFF-state nMOSFET struck by particles. In addition, the SEU hardness also reveals a non-monotonic variation feature with increasing source and drain resistance.