Influences of temperature and etching voltage on the surface morphology of photo-electro-chemical etching for silicon microchannel arrays

Abstract

The application fields of high aspect ratio Si microchannel arrays have increased considerably, for example, Si microchannel plates, MEMS devices and so on. By the method of photo-electrochemical etching (PEC), Si microchannel arrays are prepared using n-Si wafer covered by anti-corrosion layers and initiation array pits. The dark current intensity curve of an n-type silicon wafer was presented in aqueous HF. The relationship among temperature, etching voltage and carrier transportation was presented. The influences of temperature and etching voltage on the surface morphology of silicon microchannel arrays were researched. The perfect Si microchannel arrays structure with the pore depth of 297 μm, the pore size of 3 μm and the aspect ratio of 99 was obtained by the method of reducing etching voltage gradually.