Influence of Within-Die Transistor Characteristics Variation on FINFET Circuit Delay

Abstract

The increase of within-die random variation accompanying continuing advancement of the semiconductor technology necessitates variation-aware approaches in circuit design and analysis. Statistical circuit modeling becomes an important means of realizing such approaches. In this article, analytical models for the within-die random variation of the inverter, NAND and NOR circuits are developed. To analyze random variation, the effective current concept is employed wherein circuit delay is approximated by the product of the load capacitance and supply voltage over two times the effective current. The standard deviation and mean of the circuit delay are expressed as functions of the standard deviation and mean of the effective and linear transistor currents. The developed model delivers easy means of evaluating delay variation of basic circuits. The model is verified by comparison to Monte-Carlo circuit simulations for 7-nm state-of-the-art FINFET technology. Relative error for NAND2 fall/NOR2 rise mean delay is less than 9% and for standard deviation is less than 6%. Relative error for inverter rise/fall mean delay is within 8%, however, error is larger for inverter delay standard deviation. The model is convenient for analyzing the dependence of the circuit delay standard deviation on the transistor width and the supply voltage and is useful for improving technology development efficiency in achieving target circuit performance.