Influence of Thermal Stress and Kinetic Bias Stress on the Electrical Performance of Mixed Oxide Thin Film Transistors

Abstract

This study discusses thermally activated defects in the channel layer of indium zinc oxide (IZO) thin film transistors (TFTs) under electrical and thermal stress resembling practical stress scenarios. Operating temperatures of 20, 50, and 80 {degree sign}C have been chosen to establish a relation between temperature and failure mechanism. With increasing stress period, acceptor- and donor-like traps contribute towards degrading drain current and subthreshold swing. Low temperature long hour anneal for 12, 24, 36, 48 and 60 hr at 150 {degree sign}C are performed on the TFTs post fabrication to cure the defects formed during fabrication. Structures treated for 48 hr demonstrate high stability under extended kinetic stresses, maintaining a high transistor Ion/Ioff ratio of ~ 108. A physically-based mathematical model discusses the reduction in the density of acceptor-like trap states by 50 % for TFTs treated for 12 hrs, and to insignificant numbers for TFTs treated for 48 hr.