Influence of the gate thickness on the memory behavior of MFIS-FETs

Abstract

The effect of the film thickness of the ferroelectric barium strontium titanate thin films at the memory behavior of ferroelectric-gate field effect transistor (FeFET) has been studied. The films have been fabricated as metal-ferroelectric-insulator-semiconductor (MFIS) configuration using sol-gel technique. In order to investigate the memory window behavior, the C-V measurements have been carried out for the prepared samples at different applied voltage values. The results show that the memory window width increases with the increase of the film thickness, which is attributed to the grain size effect. It is found also that the memory window increases as the applied voltage increases. The leakage current of the films has been presented to study the interface behavior of the gate junction; the result shows that the leakage current increases with increasing the film thickness. Furthermore, it is found that for all the tested samples the leakage current density is of order 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . These values of the current density are relatively low, leading to good interfaces situation.