Abstract
In order to optimise the 0.5 μm CMOS technology, electromigration (EM) tests were performed at different temperature and current stresses on metal-2 line structures with 2 different anti-reflective coatings (ARC). The failure data were analysed with an in-house made software package “FAILURE”, based on Black's equation MTTF = Aj −n exp ( E a kT ). Both cases fulfill the criterium of less than 0.01% failures within 25 years under use conditions, but the Ti TiN ARC had a better EM resistance than the TiN ARC. In the case of a Ti TiN ARC a “TiAl 3”-layer was present, possibly acting as an alternative current path. This layer is formed during the thermal process steps in the 0.5 μm triple layer metallisation (TLM) processing of the wafer. This could explain the better EM resistance for the Ti TiN ARC case.
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