Influence of Source/Drain Residual Implant Lattice Damage Traps on Silicon Carbide Metal Semiconductor Field-Effect Transistor Drain I-V Characteristics

Abstract

Abstract 4H-SiC n-channel power metal semiconductor field-effect transistors (MESFETs) with nitrogen n+-implanted source/drain ohmic contact regions, with and without p-buffer layer fabricated on semi-insulating substrates exhibited hysteresis in the drain I-V characteristics of both types of devices at 300 K and 480 K due to traps. However, thermal spectroscopic measurements could detect the traps only in the devices without p-buffer. Device simulation and optical admittance spectroscopy (OAS) are used to resolve the discrepancy in the initial experimental characterization results. Device simulations and OAS suggest that, in addition to the semi-insulating (SI) substrate traps, acceptor traps due to source/drain residual implant lattice damage contribute to the hysteresis observed in the drain I-V characteristics of the devices. Simulations suggest these traps are contained in the lateral straggle of the implanted source and drain regions since the drain current largely flows between the un-gated edges of the source and drain through the volume of lateral straggle traps. Since hysteresis in I-V curves is a manifestation of the presence of defects in devices and since defects degrade carrier mobility and hence device performance, efforts should be made to minimize the source/drain lateral straggle implant damage.