Influence of Perovskite Grain Size and TiO2 Surface States to the Performance of Perovskite Solar Cell

Abstract

Introduction Currently, perovskite solar cells (PSCs) have received great curiosity from solar cell field, due to rapid improvement in their photoelectric conversion efficiencies (PCEs) from 9% to over 22% [1]. PSCs can be constructed with either invert or regular structure. In invert type, organic materials are employed as the hole transporting layer (HTL) and electron transporting layer (ETL). The PSCs with invert structure has reached PCE 20.15% [2]. The PSCs with regular structure typically employs both mesoporous and planar inorganic material of TiO2 to serve as ETL because the affinity of perovskite layers with TiO2 is generally lower than that with organic ETL. When considering the long stability, inorganic material would be better than organic material as ETL. The current best performing PSCs with mesoporous TiO2 as ETL perform PCE >22% because mesoporous TiO2 helps to support perovskite layer acting as a scaffold and make better connection with perovskite layer[1]. On the other hand, PSCs with planar TiO2 also shows PCE about 20.2%, which is lower than with mesoporous TiO2 but provides a more straightforward platform for fundamental investigations [3]. However, in planar structure, the quality of each layers is an important factor that affect overall cell performance, especially ETL [4]. However, a mechanism depending on ETL on cell performances should be investigated in detail. For ETL, various deposition methods are explored, such as spin coating, atomic layer deposition and sputtering, especially spray-coating has a great potential for the large-scale production due to the low cost and capability to obtain thin films in large areas for industrial application. The polycrystalline has grain boundaries. When having polycrystalline Si with more grain boundaries, Si solar cell shows lower performance because grain boundaries act as recombination centers for electrons and holes and become scattering centers of free carriers [5]. CuInSe2 (CIS) solar cell showed PCE about 20% without special grain boundaries passivation [6]. Similar to CIS solar cell, perovskite grain boundaries seem to have small effect on photoelectronic properties because even high efficient PSCs have smaller grain size less than 1 um. Therefore, the relationship between grain size and performance of PSCs have not been clarified clearly. Here, Kim et al. showed planar PSCs of FTO/compact TiO2/MAPbI3/spiro-OMeTAD/Au. They obtained dense MAPbI3 layers with different grain sizes ranging from ~100 to ~500 nm. With increasing grain size of perovskites, all the photovoltaic parameters were improved. As a result, the best performance was observed for the largest perovskite grain size (~500 nm) with PCE of 19.4% [7]. In this paper, we investigated the relationship between PSC performance and grain size distribution on the top of planar TiO2 by spray pyrolysis technique to construct more defined structure. SEM image from top view and cross section were observed and used to identify the grain size distribution. The surface roughness of TiO2 measured by AFM used for investigation of the relationship with perovskite grain size. These findings indicated that wide variations in the device efficiency also influence by perovskite grain size distribution in planar heterojunction structure. Experimental An around 80-100 nm thick compact-TiO2 layer was deposited on ITO by spray pyrolysis at 350, 450 and 550°C to investigate the of spray temperature (Ts) effect on compact-TiO2 surface state. Also, ethanol, propanol and 1-butanol were used as a precursor solvent with different boiling temperature (Tb) to find their effects on compact-TiO2 surface state. Next, samples were annealed at different temperatures (400, 450, 500 or 600°C) for 1 hr to study an effect of annealing temperature (Ta) as shown in Table 1. The device structure consists of; ITO/compact-TiO2/CH3NH3PbI3/Spiro-OMeTAD/Au with active area 0.5 cm2. Results and discussion In this work, planar PSCs were assembled with different ETL fabrication condition for comparison. The uniform TiO2 film without pin hole were successfully deposited by using 1-butanol as a solvent. However, the wide range variations of PCE values were observed even at the same fabrication condition. So, grain size distribution was measured and the results indicated that higher device efficiencies at the same ETL fabrication condition resulted from larger perovskite grain size distribution. The obtained dense MAPbI3 layers showed different grain sizes ranging from ~100 to ~300 nm. In addition, the relationship between roughness of TiO2 and perovskite grain size showed that the larger grain sizes were from lower roughness of TiO2 film. Therefore, higher PCEs were strongly achieved from larger perovskite grain size on planar TiO2. Figure 1