Influence of parasitic capacitances in modeling and analysis of advanced floating gate memory devices

Abstract

In this paper, we report the impact of the parasitic capacitances in the modeling and analysis of advanced floating gate (FG) non-volatile memory (NVM) devices, especially on the coupling ratio. Due to the poor accuracy of the existing capacitance model when compared to practice, an approach to include the parasitic capacitances has been established. Measurement results from two transistor (2T) Fowler-Nordheim (FN) tunneling operated flash memory show a good improvement in the model accuracy. The parasitic capacitances depend very much on the floating gate dimension, and the spacing to the neighboring elements in the flash cell array. The growing influence of the parasitic capacitances and the subsequent degradation of the existing model accuracy can be expected for the cells dimensions in future process technologies. With the accurate calculation method for the parasitic capacitances proposed in this paper, the cell characteristics can be more accurately modeled, and the degradation of the cell can be accurately studied.