Influence of micro voids in flip chip bump on electro-migration reliability

Abstract

Micro voids present at flip chip joining affect interconnection reliability. In this report, the influence of micro voids present in flip chip joining using Cu pillars bumps on electro-migration resistivity was investigated. Large voids were intentionally generated at the bump interconnection portion, and the difference in electro-migration resistivity was compared with the case with few voids. The electro-migration test was conducted under the conditions of 150 degrees C. and 40 kA/ cm2, and the direction of electron flow from the Cu pad on the substrate side to the Cu pillar side (forward direction) or from the Cu pillar side to the substrate side (reverse direction). The lifetime of the paste method sample was approximately 0.43 times shorter than that of the ball method sample in both the forward and the reverse directions. The lifetime in the reverse direction was approximately 4.3 times longer than that in the forward direction. Results from simulation of current density distribution, the lifetime expected from Black’s equation in the reverse direction was approximately 3.9 times longer than that in the forward direction, showing a relatively good agreement. On the other hand, the lifetime expected from area of the voids, it was 0.7 times shorter than without voids, which did not match the experimental data of 0.43 times. In case of presence of voids of 10 microns diameter at the solder / Cu pad interface, the current density is concentrated near the voids. And it is expected to be approximately 1.5 times higher than without voids. The lifetime was about 0.43 times longer than without voids. It was found that the presence of voids greatly affects the electro-migration lifetime.