Abstract
This paper presents an analysis of the temperature influence on Ultra Thin Body and Box (UTBB) SOI nMOSFETs with and without Ground Plane (GP) implantation and different silicon film thickness. The results obtained experimentally and by simulations show a kink in the drain current as a function of back-gate voltage due to the substrate potential drop when the ground plane is not present. The ground plane reduces the substrate potential drop, but increases the potential drop at gate and buried oxides. This study was done from room temperature up to 200oC.
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