Abstract
Time-dependent dielectric breakdown and stress-induced leakage current (SILC) behavior of a 28-nm hafnium-based high-k/metal gate n-type MOS transistors are investigated under dc and ac conditions. Compared with the constant voltage stress results under dc conditions, a decrease in device lifetime is observed for low-frequency ac stress. Degradation enhancement and SILC behavior are attributed to defect generation in the SiO2 interface layer. For high-frequency ac stress, a lifetime improvement is observed, because of reduced trap generation.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
