Abstract
This paper investigates the variation of electrical characteristic of indium gallium zinc oxide (IGZO) thin film transistors (TFTs) under gate bias stress. The devices are subjected to positive and negative gate bias stress for prolonged time periods. The effect of bias stress time and polarity on the transistor current equation is investigated and the underlying effects responsible for these variations are determined. Negative gate stress produces a positive shift in the threshold voltage. This can be noted as a variation from prior studies. Due to variation of power factor (n) from two, the integral method is implemented to extract threshold voltage (vt) and power factor (n). Effective, mobility (ueff), drain to source resistance (RDS) and constant k' is also extracted from the device characteristics. The unstressed value of n is deter-mined to be 2.5. The power factor increases with gate bias stress time. The distribution of states in the conduction band is revealed by the variation in power factor.
Highlights
Thin film transistors (TFTs) are used as switching elements in active matrix liquid crystal (LCD) and light emitting diode (LED) displays
This paper investigates the variation of electrical characteristic of indium gallium zinc oxide (IGZO) thin film transistors (TFTs) under gate bias stress
From this study we determine the effect of bias stress polarity and time on the stability of TFTs by analyzing the device characteristics
Summary
Thin film transistors (TFTs) are used as switching elements in active matrix liquid crystal (LCD) and light emitting diode (LED) displays. Owing to their high mobilities, low temperature fabrication, cost effectiveness and uniformity amorphous IGZO TFTs are a good replacement for a-Si:H TFTs [1,2]. There are two possible mechanisms responsible for device degradation. This could be due to trapping of charges in the channel/ dielectric interface due to the creation of defect states in the deep gap states of the channel dielectric interface [3,4]. The analysis of threshold voltage, sub-threshold swing, mobility, power factor and drain to source resistance variation with stress time and stress polarity reveals the underlying phenomenon behind device degradation
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