Abstract

This paper investigates the effects of the die-shift-distance (DSD) of overhang dies on residual thermal shear stress and warpage in a 5-chip stacked-die system-in-packaging (SDSiP) implementation. The proposed 5-chip SDSiP includes a single microprocessor (chip 1) and four pieces of dynamic random access memory (chips 2 to 5) with chip 4 stacked atop chip 2 and chip 5 stacked atop chip 3. Computer software based on finite element method (ANSYS) in conjunction with the measured material properties made it possible to obtain the shear stress, shear strain, warpage, and shear strain energy density (U0) within the chips in the 5-chip SDSiP. We also conducted experiments to obtain the interfacial shear stress as well as U0 between the EMC and die, which was compared with the numerical U0. When the DSD exceeded 0.4mm, the position of maximum shear stress at EMC/die interface in the 5-chip SDSiP changed from chip 4 to chip 1 due to a decrease in the rigidity of the stacked dies. Maximum warpage in the 5-chip SDSiP appeared in the top-left corner with movement in a downward direction. This effect can be attributed to mismatch in the CTE among the various materials in the 5-chip SDSiP.

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