Abstract
The performance of a LOCOS-isolated SOI MOSFET heavily depends on its back-gate characteristic, which can be affected by back-gate stress. A large voltage stress was applied to the back gate of SOI devices for at least 30 s at room temperature, which could effectively modify the back-gate threshold voltage of these devices. This modification is stable and time invariant. In order to improve the back-gate threshold voltage, positive substrate bias was applied to NMOS devices and negative substrate bias was applied to PMOS devices. These results suggest that there is a leakage path between source and drain along the silicon island edge, and the application of large back-gate bias with the source, drain and gate grounded can strongly affect this leakage path. So we draw the conclusion that the back-gate threshold voltage, which is directly related to the leakage current, can be influenced by back-gate stress.
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