Abstract

This paper proposes an inexact Baugh-Wooley Wallace tree multiplier with novel architecture for inexact 4:2 compressor optimised for realisation using reversible logic. The proposed inexact 4:2 compressor has ±1 Error Distance (ED) and 12.5% Error Rate (ER). The efficacy of the proposed reversible logic based realisation of the proposed inexact 4:2 compressor and Baugh-Wooley Wallace tree multiplier is measured in scales of Gate Count (GC), Quantum Cost (QC), Garbage Output (GO) and Ancilla Input (AI). The proposed inexact 4:2 compressor is able to reduce reversible logic realisation metrics GC, QC, GO and AI by 50%, 15%, 25% and 11.11% as compared to reversible logic realisation of exact 4:2 compressor. An 8 × 8 Baugh-Wooley Wallace tree multiplier is implemented in this paper. The accuracy metrics MED and MRED are measured for the proposed multiplier and is found to be the least among existing inexact compressor based multiplier designs. MED and MRED of the proposed multiplier is 59.16 and 0.0109 respectively. The proposed multiplier is utilised in two applications 1) image processing - one level decomposition using rationalised db6 wavelet filter bank and image smoothing and 2) Convolutional Neural Networks (CNN). The efficacy of the proposed multiplier in image processing applications is estimated by measuring Structural Similarity Index Measure (SSIM) which is found to be 0.96 and 0.84 for image decomposition and smoothing respectively. In CNN based application, the efficiency is measured in scales of accuracy and is found to be 97.1%.

Highlights

  • M AJORITY of the signal processing applications have convolutional units as its computationally intensive and performance determining operational units

  • High speed multipliers that are optimised for area and power are in great demand in real life applications involving computational units which are used in convolutional neural networks, multimedia, etc

  • The reversible logic realisation of an exact compressor is presented in Figure 7 and has four Feynman gates, one NOT gate, two BJN gates and four Peres gates with eight Ancilla Inputs (AI) and nine Garbage Output (GO)

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Summary

INTRODUCTION

M AJORITY of the signal processing applications have convolutional units as its computationally intensive and performance determining operational units. To address the need to realise low power computational units for error resilient applications, this paper proposes an inexact Baugh-Wooley Wallace tree multiplier. In the implementation of conventional Wallace tree multiplier, a series of full adders are used to generate the final carry and sum in a column with multiple partial product bits. This method has varying number of bits to be added in each column, which demands a complex circuit for accumulation. Full adders are for groups of three bits and half adders for groups of two bits

BAUGH-WOOLEY WALLACE TREE MULTIPLIER
INEXACT 4 : 2 COMPRESSOR
HALF ADDER
FULL ADDER
EXACT 4 : 2 COMPRESSOR
RESULTS
Design
CNN APPLICATION
CONCLUSION
Full Text
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