Industry session IV: 3DIC and integrated voltage regulators

Abstract

Cache-coherent multi-core server processors require maximum memory bandwidth and minimum cache latency. The performance of conventional 2D single die processors is limited by the number and speed of memory IO channels and by long-range on-die interconnect delay. This technological research investigation explores 3DIC stacked die as a means to avoid the spatial and latency limitations of a single 2D die. By expanding vertically into the third dimension, lateral mm can be traded for vertical microns of interconnect. Heterogeneous die stacking enables optimizing the top die for cores and cache by moving functionality that does not need the highest performance silicon, such as serdes IO, to the base die in an older technology. The top die can then be simplified by removing the IO transistors, esd, and analog features such as precision resistors etc to the base die. Combining two dies face-to-face adds the routing resources of the full BEOL metal stack of the base die to that of the top die. Classical 3DIC techniques such as block folding further reduce critical path latency. Increasingly important implemention of software-in-silicon for database acceleration also requires full memory bandwidth and minimal latency L3 cache access. The extra silicon area in the base die can implement these features with an FPGA or optimized macros. This extra area could also be used to implement a large L4 cache with greatly reduced latency compared with off-die, 2.5D or MCM options. In addition, 3DIC optimally implements integrated voltage regulators in the base die to provide very short range highly regulated power delivery to voltage domains in both die. This greatly simplifies system-level power delivery by supplying 2x the voltage at 1/2 the current without stringent regulation. The board and package requirements can be relaxed as there is less I⁁2R power loss. The IVRs in the base die deliver minimum ripple, allowing lower Vmin, saving power and provide much faster load transient response and faster DVFS. In these ways, 3DIC offers increased performance and more functionality than possible with a single-level 2D die.