Industrial strength formal verification techniques for hardware designs

Abstract

The past decade has seen tremendous progress in the application of formal methods for hardware design and verification. While a number of different techniques based on BDDs, symbolic simulation, special-purpose decision procedures, model checking, and theorem proving have been applied with varying degrees of success, no one technique by itself has proven to be effective enough to verify a complex register-transfer level design, such as a state-of-the-art microprocessor. To scale up formal verification to industrial-scale designs it is necessary to combine these complimentary techniques within a general logical environment that can support appropriate abstraction mechanisms. The Prototype Verification System (PVS) is an environment to support the exploration of such a combined approach to verification. PVS is designed to exploit the synergies between language and deduction, automation and interaction, and theorem proving and model checking. This paper gives an overview of PVS and describes some of the major applications of PVS.