Inductance/area/resistance tradeoffs in high performance power distribution grids

Abstract

The design of high integrity, area efficient power distribution grids is of immediate practical importance as the portion of on-chip interconnect resources dedicated to power distribution networks in high performance integrated circuits has greatly increased. To optimize the process of allocating on-chip metal resources, inductance/area/resistance tradeoffs in high speed power distribution grids are explored. Two tradeoff scenarios in power grids with alternating power and ground rails are considered. In the first scenario, the area occupied by the grid lines is maintained constant and the grid inductance versus grid resistance tradeoff is evaluated as the width of the grid lines varies. In the second scenario, the metal area of the grid is maintained constant and the grid inductance versus grid area tradeoff is investigated. In both cases, the grid inductance increases almost linearly with line width, rising more then eightfold for a tenfold increase in line width. The grid resistance and grid area, however, decrease relatively slowly with line width. This decrease in grid resistance and area is limited to a factor of two under assumed interconnect characteristics.