In-die mask registration for multi-patterning

Abstract

193nm immersion lithography is the mainstream production technology for the 20nm and 14nm logic nodes. Considering multi-patterning as the technology to solve the very low k1 situation in the resolution equation puts extreme pressure on the intra-field overlay, to which mask registration error is a major error contributor. The International Technology Roadmap for Semiconductors (ITRS) requests a registration error below 4 nm for each mask of a multi-patterning set forming one layer on the wafer. For mask metrology at the 20nm and 14nm logic nodes, maintaining a precision-to-tolerance (P/T) ratio below 0.25 will be very challenging. Mask registration error impacts intra-field wafer overlay directly and has a major impact on wafer yield. We will discuss a solution to support full in-die registration metrology on reticles.