Abstract
Network-on-Chip (NoC) architectures have been proposed as a promising alternative to classic bus-based communication architectures. In NoC design, power efficiency is a crucial concern that runs through the whole synthesis process, such as topology generation, mapping, routing, et al. However, it is hard to converge at the final layout generation stage since different stages have different design objects. In this paper, we present an incremental power-aware layout optimization method based on a Mixed Integer Linear Programming (MILP) model at post-layout stage in NoC design. Experimental results show that our optimization flow can achieve 23.3% power reduction on wires with a reasonable runtime while both the area and chip performance would not compromise.
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