Increasing Test Coverage in a VLSI Design Course

Abstract

VLSI Designers know so little about testing that the large, multi-national corporations frequently higher test experts to advise their designers on test problems. The companies even pay a higher salary to the testing experts than to their VLSI Designers. The author's position is that three lectures in every VLSI Design course should be devoted to test. The first lecture would touch briefly on Test Economics, in order to motivate the students to take an interest in testing problems and costs. This lecture would also include introductory Fault Modeling for stuck-faults, delay-faults (transition and path), bridging faults, MOS Transistor Faults, and IDDQ Faults. Industry uses all of these faults in production testing. The second lecture would cover Fault Simulation, as well as Combinational and Sequential automatic test-pattern generation (ATPG) and the reason for redundancy removal (to avoid masking of testable faults). The focus of this lecture should not be on the various algorithms, but rather on the test generation and fault simulation process. This will train the students in redundancy removal techniques, and teach them how to facilitate test generation by removing testability problems from their designs. The final lecture should be on design for testability (DFT). This would cover Full and Partial Scan, as well as the JTAG 1149 Boundary Scan Standard. Scan is included because a very high percentage of designs will employ some form of scan. In addition, built-in self-testing (BIST) should be introduced in this lecture, but details would be omitted. BIST is important, because industry and leading academics project that BIST may appear in 90% of the chips in 11 years. If additional time is available, I would suggest a fourth lecture on Testability Measures, and how they can be used by the designer, to eliminate test generation problems, predict fault coverages, and accelerate ATPG programs.