Increasing interposer utilization: A scalable, energy efficient and high bandwidth multicore-multichip integration solution

Abstract

With the increase in number of processing chips in platform based computation intensive systems such as servers, a seamless, scalable, energy efficient and high bandwidth interconnection network is required. Newly envisioned silicon interposers with Network-on-Chip (NoC) interconnection framework have emerged as an energy efficient technology for 2.5D integration of multiple processor and memory chips, where multiple chips are mounted on another die called the interposer and are interconnected using the metal layers of the interposer die. However, conventional interposer based multichip integration is limited to edge-to-edge connections between the adjacent dies leaving the interposer's routing resources underutilized. In this paper, we propose large scale utilization of the available abundant interposer resources for multichip integration by implementing a hypercube interconnection architecture in an interposer for chip-to-chip communication. Through system level simulations, we demonstrate that such multichip system integrated with interposer can provide high bandwidth and energy-efficient communication under various traffic patterns.