Increase in the Rate and Discretization of the Kinetics of Isothermal Surface Generation of Minority Charge Carriers in Metal–Insulator–Semiconductor Structures with a Planar-Inhomogeneous Insulator

Abstract

Surface generation of minority charge carriers in silicon metal-oxide-semiconductor (MOS) structures is efficient only at the initial recombinationless stage. Quasi-equilibrium between surface generation centers and the minority-carrier band is established in a time t ∼ 10−5 s. In the absence of other carrier generation channels, an equilibrium inversion state at 300 K would need t = t∞ > 103 years to become established. In fact, the time t ∞ is much shorter, due to excess-carrier generation via centers located at the SiO2/Si interface over the gate periphery. This edge-related generation can easily be simulated in an MOS structure with a single gate insulated from Si by oxide layers of various thicknesses. At gate depleting voltages V g , the role of the periphery is played by a shallow potential well under a thicker oxide, and the current-generation kinetics becomes unconventional: two discrete steps are observed in the dependences I(t), and the duration and height of these steps depend on V g . An analysis of the I(t) curves allows determination of the electric characteristics of the Si surface in the states of initial depletion (t = 0) and equilibrium inversion (t = t∞), as well as the parameters of surface lag centers, including their energy and spatial distributions. The functionally specialized planar inhomogeneity of a gate insulator is a promising basis for dynamic sensors with integrating and threshold properties.