Abstract
Improvement of digital FIR filter is vital in the field of Digital Signal Processing in order to reduce the area, delay and power. Multiplication and Accumulation (MAC) unit of Finite Impulse Response (FIR) filter has been designed using efficient multiplier and adder circuits for optimized APT (Area,Power and Timing) product. In this paper, the design of direct form FIR filter with efficient MAC unit has been presented. Initially, full adder and half adder structures are shrunk down by reducing number of gates. These compact full adder and half adder structures are incorporated into Wallace Multiplier and Improved Carry-Save Adder. The proposed 16-bit Carry-Save Adder has been improved by splitting into four parallel phases. Consequently the delay of enhanced Carry- Save Adder is reduced. Generation of carry output is performed using number of OR gates in a sequential manner. All these enhanced architectures are incorporated into the Digital FIR Filter to reduce the area, delay and power utilization.
Highlights
Finite impulse response digital filter is the most important component in communication systems and applica-How to cite this paper: Chinnapparaj, S. and Somasundareswari, D. (2016) Incorporation of Reduced Full Adder and Half Adder into Wallace Multiplier and Improved Carry-Save Adder for Digital Finite Impulse Response (FIR) Filter
From the results, Improved Carry-Save Adder offers 25% area reduction and 15% delay reduction compared to conventional Carry-Save Adder
Total equivalent LUT in case of enhanced Wallace multiplier with CSA is 162, which is improved to 152 using Improved Carry-Save Adder based Wallace Multiplier
Summary
How to cite this paper: Chinnapparaj, S. and Somasundareswari, D. (2016) Incorporation of Reduced Full Adder and Half Adder into Wallace Multiplier and Improved Carry-Save Adder for Digital FIR Filter. (2016) Incorporation of Reduced Full Adder and Half Adder into Wallace Multiplier and Improved Carry-Save Adder for Digital FIR Filter. Regular Wallace and reduced Wallace Multipliers are designed using different high speed adders [6] It consumes more area, power and less delay [7]-[9]. Described works have been focused on reducing the power consumption and improving the configuration of filter coefficients All those architectures have more complexity, because of using traditional hardware structures to perform multiplication and accumulation functions. The redundant Boolean logical expressions of half adder and full adder are identified to optimize the digital signal processing operations. Because Enhanced Wallace Multiplier with Improved Carry-Save adder is incorporated into proposed FIR filter.
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