Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates

Abstract

Decreased power supply levels have reduced the tolerance to voltage changes within power distribution networks in CMOS integrated circuits. High on-chip currents, required to charge and discharge large on-chip loads while operating at high frequencies, produce significant transient i>IR voltage drops within a power distribution network. These transient i>IR voltage drops can affect the propagation delay of a CMOS logic gate, creating delay uncertainty within data paths. Analytical expressions characterizing these transient i>IR voltage drops are presented in this paper. The peak value of these transient i>IR voltage drops is within 6% as compared to SPICE. Circuit- and layout-level design constraints are also discussed to manage the peak value of the transient i>IR voltage drops. The propagation delay of a CMOS logic gate based on these analytical expressions is within 5% of SPICE while the estimate without considering transient i>IR voltage drops can exceed 20% for a 20 Ω power line.