Abstract

III–V n-channel MOSFETs based on In x Ga1− x As are evaluated for low-power (LP) technology at a sub-10-nm technology node. Aggressive design rules are followed, while industry-relevant FinFET architecture is selected. We show, for the first time, quantum confinement-related leakage and performance tradeoff done self-consistently in performance evaluation using an in-house developed semiclassical tool. In this paper, we focus on In0.53Ga0.47As as the channel material, as it has been investigated heavily in the literature. Furthermore, it has a bulk bandgap $E_{G}$ similar to that of Ge, another highly studied complementary p-FET channel material. Higher In-content results in lower $E_{G}$ and hence larger band-to-band tunneling (BTBT) current, resulting in more stringent design requirements for LP applications. A comparison is done with the state-of-the-art tensile-Si (t-Si) technology, with roughly 2-GPa stress, under similar constraints ( $L_{G}$ , design rules). Thus, we show that while for 0.75 V operation, In0.53Ga0.47As performance is limited by the BTBT and fails to outperform t-Si, it starts to perform better than t-Si below 0.7 V. $V_{{\rm {DD}}}$ scaling further results in an increased performance gap between the two material systems.

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