In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization

Luis Mendes,Nuno Lourenco,Joao Caldinhas Vaz,Fabio Passos,Ricardo Martins

doi:10.1109/access.2021.3078240

Luis Mendes, Nuno Lourenco + Show 3 more

Open Access

https://doi.org/10.1109/access.2021.3078240

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Abstract

Low-noise amplifiers (LNAs) play a significant role in modern millimeter-wave (mmWave) integrated circuits for fifth-generation (5G) communications systems. However, the proper analysis of their design tradeoffs that allow for a realistic topology comparison is impractical. The many conflicting specifications that must be carefully balanced make the problem intractable. In this paper, the 148-dimensional performance spaces of three 28-GHz LNAs are fully explored for a 65-nm CMOS technology node, using an enhanced electronic design automation tool. One- and two-step many-objective optimizations provide up to 1024 different LNAs for each of the considered topologies, enabling a thorough assessment of their performance tradeoffs. The first optimizes all the design parameters at once. In contrast, the latter optimizes the spiral inductors in a first step. Then, in a second step, it optimizes the remaining parameters. The resulting designs provide new insight on the tradeoffs between gain, noise figure, power, and circuit’s footprint for current 5G specifications. Process, voltage, and temperature corners impact the LNAs’ performance severely. Still, the optimization shows that proper sizing of these topologies compete with the most-recent mmWave LNAs and can play a role in the challenging 28-GHz band.

Highlights

An enormous investment has been made in the past recent years to the rapid development and prototyping of 26/28-GHz transceiver front-end CMOS interfaces to keep up with the fifth-generation (5G) communication systems demands
The results show that LNA3 (LowNF variant) can achieve low noise figures (NFs) (2.76-dB) and high gain (11-dB) at the expense of slightly higher power consumption (12.64-mW), lower than those obtained in [24] and [25]
The sizing results of three 28-GHz Low-noise amplifiers (LNAs) were presented for a 65-nm technology node, where electronic design automation (EDA) tools balance the design tradeoffs comprehensively over all the performance figures, and, through several different processes, voltage, and temperature corners, without manual intervention

Summary

Introduction

An enormous investment has been made in the past recent years to the rapid development and prototyping of 26/28-GHz transceiver front-end CMOS interfaces to keep up with the fifth-generation (5G) communication systems demands. In order to aid designers, some analytical methodologies have been used in order to reach initial solutions, they are transistor-oriented and not specification-oriented and the methodologies may not lead to optimal designs directly (e.g., gm/Id methodologies) [5]-[7]. Such methods became more difficult to apply in modern multi-dimensional design performance spaces. At lower frequency ranges of the radio spectrum up to several gigahertz, the application of electronic design automation (EDA) tools [8] was critical in exploring complex design spaces These EDA tools use an optimization engine to interact with the circuit simulator and size the circuits [9]-[18]. Reports of applying these methodologies to VOLUME XX, 2017

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