In Depth Analysis of 3D NAND Enablers in Gate Stack Integration and Demonstration in 3D Devices

Chi Lim Tan ,S Lavizzari,N Jossart,A Peter ,Senthil Vadakupudhu Palayam ,N Heylen ,Diana Tsvetanova ,Tao Zheng ,Romain Delhougne ,Harold Dekkers ,Laura Nyns ,Lieve Teugels ,Farid Sebaai ,Patrick Ong ,Pasquale Mennella ,A Arreghini ,G Van Den Bosch ,K Devriendt ,Tom Raymaekers ,Guglielma Vecchio ,Pieter Blomme ,Bart Schepers ,Vasile Paraschiv ,L Breuil ,A Furnemont

doi:10.1109/imw.2017.7939090

In Depth Analysis of 3D NAND Enablers in Gate Stack Integration and Demonstration in 3D Devices

Chi Lim Tan , S Lavizzari + Show 23 more

https://doi.org/10.1109/imw.2017.7939090

Copy DOI

Publication Date: May 1, 2017

Citations: 4

Affiliation: IMEC

#Gate Stack Integration #3D NAND + Show 8 more

Abstract
Full-Text PDF
Similar Papers

Abstract

An in-depth analysis of gate stack enhancements that enable multi-Gb 3D NAND products is performed. Alternative charge trapping layer, enhanced tunnel oxide based on the VariOT concept and metal gate with Al2O3 high-k liner have been proposed and evaluated. The most promising solutions were successfully integrated in 3D devices. Integration challenges of the replacement gate approach, required to have metal gate in 3D NAND, are also analyzed and discussed in detail.

Full Text